We released a new FPGA design for phase noise measurements.
Using a Koheron Alpha250, we compared the phase noise of 40 MHz signals from 3 different noise sources: a Red Pitaya STEMLab 125-14, another Koheron Alpha250, and a 120 MHz signal generator (Keysight 33622A):
The higher phase noise of the Red Pitaya can be explained by the fact that the Red Pitaya DAC is clocked from a phase-locked loop inside the FPGA, instead of an external PLL.
The source code is available on GitHub for the Alpha250 and the Red Pitaya.
