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Reference Designs for Zynq®
Open source reference designs for Xilinx Zynq® development boardsADC / DAC with DMA
Set 1 DAC channel, get 1 ADC channel using DMA (8 MS at 250 MSps)
version: 0.2.0
ADC / DAC with BRAMs
Set 2 DAC channels, get 2 ADC channels using BRAMs (64 kS at 250 MSps)
version: 0.2.0
