From prompt to instrument

We described an instrument to Codex (GPT-6-Astra medium). It wrote the FPGA logic, C++ driver and Python script, ran simulations, built the design with Vivado, and tested it on an ALPHA250. The first hardware acquisition worked.

Our request, condensed from the discussion:

>> I have an ALPHA250 connected to the network,
   with DAC0 connected to ADC0.
   Start from alpha250/adc-dac-dma. Use the full 128 MiB
   buffer to capture 64 Mi samples from ADC0.
   Generate a logarithmic sine sweep directly on the FPGA,
   configurable from Python. Plot the measured magnitude
   and phase.
   Ask questions if needed, then implement, simulate,
   build and test on the board.

We discussed the waveform and frequency range. Codex handled the implementation, using Koheron SDK's existing board support, DMA example and Python interface.

The resulting instrument generates a continuous chirp at 250 MS/s and records 268 ms of ADC data. Python reconstructs the digital excitation and computes FFT(ADC) / FFT(reference). Capturing and downloading the full 128 MiB took about 2.4 seconds.

We connected a low-pass filter. Relative to direct loopback, it measured a −3 dB cutoff near 25.7 MHz and about 59 dB attenuation at 50 MHz.

Next, we connected a 10.7 MHz band-pass filter and asked for a narrower sweep:

chirp = Chirp(start_hz=8.7e6, stop_hz=12.7e6, duration=0.250)
adc = driver.acquire(chirp)

No FPGA rebuild. Compared with the original 500 Hz–110 MHz sweep, concentrating the excitation lowered the measured stopband floor by 14–15 dB, without averaging. The measured −3 dB bandwidth was 294 kHz.

The complete example includes the source, tests and implementation limits. Pick an SDK example close to what you need, describe your hardware and the instrument you want, and let Codex work from there.

Only have a Red Pitaya on hand? Ask Codex to adapt the example.