Can I change the ALPHA250 RF ADC and DAC sampling rate?

Yes. The RF ADC and RF DAC sampling rates are configured through the programmable clock generator.

The configuration is implemented in the ALPHA250 clock-generator driver.

Changing the sampling rate requires modifying the FPGA instrument configuration. See this example and the 40 MHz example.

The RF ADC and RF DAC support up to 250 Msps; some reference designs use a lower rate, for example 200 Msps. See the ALPHA250 user guide for the separate RF and precision converter descriptions.