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250 MSPS acquisition board

PRODUCTS > FPGA > 250 MSPS ACQUISITION BOARD
ALPHA250 250 MSPS FPGA Zynq board
ALPHA250 250 MSPS FPGA Zynq board ALPHA250 Functional diagram ALPHA250 noise floor ALPHA250 distortion (DAC and ADC) ALPHA250 ADC crosstalk ALPHA250 DAC crosstalk ALPHA250 phase noise

The ALPHA250 is a programmable board built around a Zynq 7020 SoC. It features a 100 MHz RF front end with 14-bit ADCs and 16-bit DACs, at 250 MSPS. The RF channels are clocked by a dual PLL, ultra-low jitter clock generator. It includes a 4-channel 24-bit ADC and a 4-channel 16-bit DAC. The board comes with a comprehensive, open source, FPGA / Linux reference design.

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Includes

  • 12 V 1.5 A power supply
  • Micro-SD card with pre-installed OS

Specifications

ALPHA250 ALPHA250-4
Programmable logic, processor and memory
System On Chip Zynq 7020 XC7Z020-2CLG400I Zynq 7020 XC7Z020-2CLG400I
Memory 512 MB of DDR3L SDRAM 512 MB of DDR3L SDRAM
Processor ARM dual-core CPU (Cortex-A9) ARM dual-core CPU (Cortex-A9)
100 MHz low-noise RF front-ends
RF ADC 2 channels, 14-bit, 250 Msps, DC coupled 4 channels, 14-bit, 250 Msps, DC coupled
RF DAC 2 channels, 16-bit, 250 Msps, DC coupled
Input to output latency 90 ns
Input / Output 1 Vpp, 50 Ω 1 Vpp, 50 Ω
Ultra-low jitter clock for RF ADC, DAC and FPGA
Clock generator Dual loop PLL, 100-fs RMS jitter (12 kHz to 20 MHz) Dual loop PLL, 100-fs RMS jitter (12 kHz to 20 MHz)
On-board VCXO 160 dBc / Hz @ 10 kHz 160 dBc / Hz @ 10 kHz
Reference clock inputs FPGA, external clock or internal crystal oscillator FPGA, external clock or internal crystal oscillator
On-board TCXO 10 MHz, 280 ppb 10 MHz, 280 ppb
Precision analog monitoring and control
Precision ADC 4 channels, 24-bit 4 channels, 24-bit
Precision DAC 4 channels, 16-bit 4 channels, 16-bit
Voltage reference 2.5 V, low-drift (3 ppm/°C) 2.5 V, low-drift (3 ppm/°C)
Temperature sensor ±0.2 °C accuracy ±0.2 °C accuracy
Other
Connectivity 10/100/1000 Ethernet, USB 2.0, USB-UART 10/100/1000 Ethernet, USB 2.0, USB-UART
General purpose I/O 3V3 16 FPGA I/Os, 8 user LEDs 1V8 16 FPGA I/Os, 8 user LEDs
Outside Dimensions 113 mm x 108 mm x 27 mm 113 mm x 108 mm x 27 mm
Software
OS Ubuntu 16.04 Ubuntu 16.04
Reference designs FFT Analyzer, ADC / DAC with BRAMs, ADC / DAC with DMA, Phase noise analyzer, Loopback FFT Analyzer, ADC with BRAMs

Characterization

Noise floor

The RF ADC and DAC noise floors were characterized with this script available on GitHub. The input referred voltage noise density of the ADC is about 13 nV/√Hz. DAC voltage noise density is about 23 nV/√Hz (19 nV/√Hz after subtraction of the ADC noise floor).

ALPHA250 Noise floor

Below is the representation of the noise floor for the 4 ADC version (ALPHA250-4) inputs (50 ohm terminated):

ALPHA250-4 Noise floor

ADC front end frequency response

ALPHA250-4 frequency response
Frequency response of the ALPHA250-4 analog front ends

Distortion

A 1 Vpp sine wave between 100 kHz and 40 MHz was send by DAC0 and measured by ADC0 (see script). The figure below shows the amplitude of the second and third harmonic, relative to the fundamental frequency:

ALPHA250 distortion (ADC and DAC)

Distortion performance is limited by the DAC. ADC distortion (HD2 and HD3) stays under -80 dB up to 40 MHz.

Crosstalk

The crosstalk between the 2 ADC channels was characterized with the following script. The crosstalk is under -95 dB up to 120 MHz.

ALPHA250 ADC crosstalk

The crosstalk between the two DAC channels is shown below:

ALPHA250 DAC crosstalk

Phase Noise

The phase noise of a 10 MHz OCXO reference clock (from Textronix MCA 3027) against the internal TCXO was measured with the Phase Noise Analyzer reference design:

ALPHA250 Phase Noise

Input to output latency

Using the loopback reference design, we observe the delay between a pulse in input (green) and the reproduced pulse at the output (yellow) for the ALPHA250 - 2 ADC, 2 DAC version:

ALPHA250 latency

Loopback latency is 90 ns, corresponding to a π/4 phase shift at 1.4 MHz.

Revision history

  • 2: October 2018 - Improved DAC crosstalk.

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ALPHA250
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